Advanced Verification Techniques for High-Performance Computing Chips
Author(s): Niranjana Gurushankar
Publication #: 2412007
Date of Publication: 09.01.2021
Country: USA
Pages: 1-6
Published In: Volume 7 Issue 1 January-2021
DOI: https://doi.org/10.5281/zenodo.14281923
Abstract
High-Performance Computing (HPC) chips demand advanced verification techniques to ensure correctness and performance. This paper explores methodologies addressing the challenges posed by massive parallelism and complex architectures. We investigate formal verification, hardware acceleration for simulation and emulation, and emerging techniques like constrained-random verification and machine learning for test generation. The paper will examine the challenges associated with verifying HPC chips , considering its technical, linguistic. The paper will also present future directions for these challenges.
Keywords: High Performance Computing, Computer Architecture, Verification Techniques, Formal Verification, Emulation, FPGA, Semiconductor, Machine Learning, Software Validation, Chip Validation, Performance
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