Abstract

The diminished-one modulo 2ⁿ+1 addition is an important arithmetic operation for a high-performance residue number system. This paper, is an attempt to implement a new circular-carry-selection (CCS) technique for modulo 2ⁿ+1addition in the diminished-one number domain. The architecture design of CCS modular adder is simple and regular for various bit-width inputs. The proposed CCS diminished-one modulo adder has been introduced and developed to derive the most compromising design in terms of area, delay and power. For a large bit-width requirement, this CCS modular adder is realized by the combination of CCS addition blocks, CCG and MUX to lead into the simple and efficient. The VLSI implementation of CCS modular adder indeed has better area-delay and delay-power performances over conventional designs.